Design and Implementation of IEEE-754 Decimal Floating Point Adder, Subtractor and Multiplier
S. Murali1, B. Srinivas2
1S. Murali,  Department of Electronics and Communication College of Engineering, Vizianagaram, India.
2B. Srinivas,  Dept. of Electronics and Communication of Engineering, Vizianagaram, India.
Manuscript received on September 27, 2014. | Revised Manuscript received on October 05, 2014. | Manuscript published on October 30, 2014. | PP: 161-166  | Volume-4 Issue-1, October 2014. | Retrieval Number:  A3502104114/2013©BEIESP

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Abstract: This paper describes the development of a Decimal Floating Point adder, subtractor multiplier and division in verilog with the help of Model Sim and will be synthesized by using Xilinx tools. These are available in single cycle and pipeline architectures and fully synthesizable with performance comparable to other available high speed implementations. The design is described as graphical schematics and code. This representation is very valuable as allows for easy navigation over all the components of the units, which allows for a faster understanding of their inter relationships aspects of a Floating Point operation. The presented DFP adder, subtractor supports operations on the decimal 64 format and our extension is decimal floating point multiplier. point design is extended to support floating-point mu by adding several components including exponent generation, rounding, shifting, and exception handling. And DFP multiplier is compared with the booth multiplier technique.
Keywords: DFP, Booth multiplier, IEEE 754 Floating point multiplication.