Performance Assessment of Different VLSI Architectures for Data Comparators for Cost-Effective Sorting Networks
Geetha V1, Anbumani V2, Ragakavya K3, Navaladi P4, Ponraj S5
1Geetha V, Assistant Professor, Department of ECE, Kongu Engineering College, Perundurai, Erode.
2Anbumani V, Assistant Professor, Department of ECE, Kongu Engineering College, Perundurai, Erode.
3Ragakavya K, UG Student, Department of ECE, Kongu Engineering College, Perundurai,Erode.
4Navaladi P, UG Student, Department of ECE, Kongu Engineering College, Perundurai, Erode.
5Ponraj S, UG Student, Department of ECE,Kongu Engineering College, Perundurai, Erode.
Manuscript received on September 23, 2019. | Revised Manuscript received on October 15, 2019. | Manuscript published on October 30, 2019. | PP: 5485-5490 | Volume-9 Issue-1, October 2019 | Retrieval Number: A2010109119/2019©BEIESP | DOI: 10.35940/ijeat.A2010.109119
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Noise removal is one of the major requirements in image, speech and signal processing applications. Impulse noise removal in image processing uses median filters. For edge preservation in image processing this acts as one of the best alternative non-linear technique to linear filtering. Real time hardware implementation of median filters has major concern of sorting networks. Efficient VLSI implementation of sorting network in terms of hardware complexity is of greater importance. This work provides a comparison of existing six data comparators and also proposes three modified data comparators in terms of their hardware complexity, area, power and speed. All the comparators were designed using verilog HDL and were targeted for xa6slx4-3-csg225using Xilinx ISE 9.2i FPGA design suite. From the results Modified Twos Complement Based Data Comparator is the minimum area required architecture with maximum combinational path delay and also with minimum number of LUTs used. The drawback of this architecture is the maximum memory requirement. The Modified Multiplexer Based Data Comparator and Modified Decoder Based Data Comparator architectures are suitable for memory efficient design.
Keywords: Impulse noise, non-linear filtering, VLSI, data comparator.