Nano Machine-based Hybrid 3D Network-on-Chip (NoC) using 18nm tsmc Technology
K.Balamurugan1, R.Shijukumar2

1Dr.K.Balamurugan *,Professor, Electronics and Communication Engineering at Swarnandhra College of Engineering and Technology, Narsapur, Andhra Pradesh, India.
2R. Shijukumar, Senior R&D Engineer, Firmtech, Thiruvanathanpuram, Kerala, India.
Manuscript received on September 23, 2019. | Revised Manuscript received on October 15, 2019. | Manuscript published on October 30, 2019. | PP: 7052-7055 | Volume-9 Issue-1, October 2019 | Retrieval Number: A1906109119/2019©BEIESP | DOI: 10.35940/ijeat.A1906.109119
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Abstract: Network-on-Chip paradigm is an emerging technology that provides communication between the Intellectual Property cores in System-on-Chip (SoC). The drastic development of nanotechnology supports the making of Intellectual property cores with small area, less power dissipation, improvement in latency and achieves high speed. The neural systems that emulate biological sensory capability on reconfigurable hardware are the key requirement in the field of Neuro-Engineering. Nano-neural connectivity technique is highly needed in order to implement reconfigurable Neural Networks (NNs) on-chip. This paper proposes a novel Nano Machine based Hybrid 3D Network-on-Chip for the emulation of a third-generation (3G) Neural Network model called Spiking Neural Network (SNN). This Hybrid Network-on-Chip uses a Nanomachine Transceiver with Carbon nanotube antenna which uses the novel pulse-based technique to transfer the packets between the subnet of NoC to reduce the latency. The experimental result of this work shows the improvement in latency of Nano machine-based NoC compared to the previously reported work for 18 nm TSMC technology.
Keywords: Network-on-Chip (NoC), System-on-Chip (SoC),CNT antenna, Wired Router, Wireless Router.