Design and Performance Analysis of Low Power High Speed 4×4 CNTFET Binary Content Addressable Memory Array
A. Gangadhar1, K. Babulu2

1A.Gangadhar*, Research Scholar, ECE Department, JNTUK, Kakinda, India.
2K.Babulu, Professor, ECE Department, JNTUK, Kakinda, India.
Manuscript received on September 11, 2019. | Revised Manuscript received on October 20, 2019. | Manuscript published on October 30, 2019. | PP: 5962-5965 | Volume-9 Issue-1, October 2019 | Retrieval Number: A1335109119/2019©BEIESP | DOI: 10.35940/ijeat.A1335.109119
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Abstract: In this paper, Carbon Nanotube Field Effect Transistor (CNTFET) based Binary Content Addressable Memory (BCAM) array is presented. The CAM array comprises of address decoders, encoders, data drivers and BCAM cells. Performance analysis is carried for 4X4 BCAM array. Each BCAM cell is designed based on adiabatic logic with optimum CNTFET parameter for low power and high speed applications. The performance of proposed BCAM array is analyzed for average power, peak power and search delay. The proposed CNTFET based BCAM array show improvement in the performance compared to that of complementary metal oxide semiconductor (CMOS) based BCAM array. The average power and peak power of the proposed 4×4 CNTFET BCAM array are in the range of micro watt (µW) while it is in the range of milli watt (mW) for CMOS based BCAM array. The search delay of the proposed 4X4 CNTFET BCAM array is improved by 32.3% compared to that of CMOS based BCAM array. All simulations are conducted for both CNTFET and CMOS based BCAM cells, BCAM array in HSPICE at 32 nm technology.
Keywords: Carbon nanotube field effect transistor, 4×4 content addressable memory array, Optimum parameter set.