Design And Implementation of Low-Power, High-Performance 2-4- and 4-16-Line Decoders using Adiabatic Logic Circuits
B. Srikanth1, M. Sri Hari2, D. Praveen Kumar3, G. Shravan Kumar4

1B. Srikanth*, ECE department, Vardhaman College of Engineering, JNTU Hyderabad, India.
2M. Srihari, ECE department, Vardhaman College of Engineering, JNTU Hyderabad, India.
3D. Praveen Kumar ECE department, Vardhaman College of Engineering, JNTU Hyderabad, India.
4G. Shravan Kumar, ECE department, MLR Institute of Technology, JNTU Hyderabad, India.
Manuscript received on September 22, 2019. | Revised Manuscript received on October 20, 2019. | Manuscript published on October 30, 2019. | PP: 2896-2901 | Volume-9 Issue-1, October 2019 | Retrieval Number: A1179109119/2019©BEIESP | DOI: 10.35940/ijeat.A1179.109119
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Abstract: In the present emerging field for the research, the reduction of power has become a major design problem in VLSI technology. As the size of the system shrinking gradually it has become the one the prime concerns in the design of decoders. The main purpose of this paper is to minimize the power and delay capabilities comparison with ordinary CMOS design. To avoid power reduction by introducing a different technique. In this paper we are approaching the adiabatic circuit has been introduced. The power dissipation in the adiabatic circuits can be minimized when compared to conventional CMOS logic. The designing of decoders with the adiabatic logic can reduce the power average power by 10.80% and delay by 21%, 23% and 24% at different voltage levels compared to the conventional CMOS. Finally, Spice simulation results show the comparison results between the existing CMOS decoders and the proposed adiabatic logic-based decoders at 32nm technology in all cases.
Keywords: CMOS Logic, Line Decoders, Adiabatic Logic, Low-Power, Performance, and Simulations.