Leakage Current Alleviation Techniques for SRAM Cell
Muralidharan Jayabalan1, Aswini Valluri2
1Dr. Muralidharan Jayabalan, Associate Professor, Department of Electronics and Communication Engineering, VFSTR Deemed to be University, Vadlamudi (A.P), India.
2Aswini Valluri, Ph.D Research Scholar, Department of Electronics and Communication Engineering, VFSTR Deemed to be University, Vadlamudi (A.P), India.
Manuscript received on 23 November 2019 | Revised Manuscript received on 17 December 2019 | Manuscript Published on 30 December 2019 | PP: 112-114 | Volume-9 Issue-1S5 December 2019 | Retrieval Number: A10271291S52019/19©BEIESP | DOI: 10.35940/ijeat.A1027.1291S52019
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Due to the tremendous increase in the call of handheld devices like mobile, iPods and tablets; certain applications like space and biomedical, it is necessary to have low power consuming digital systems. As a crucial part in digital systems,Static Random Access Memory(SRAM) should consume low power since it occupies about 70% of the total chip area. As the technology is shrinking, SRAM’s leakage power in standby condition is becoming a most critical concern for the low power applications. This paper gives a study of different leakage components present in SRAM and discusses about various current reduction techniques which include Gated VDD, MTCMOS, Dual threshold and Transistor Stacking.
Keywords: SRAM, Leakage Power, Gated VDD, MTCMOS, Dual Threshold, Transistor Stacking.
Scope of the Article: Knowledge Engineering Tools and Techniques