Design of Parity Preserving Reversible DIF-FFT using 90nm Technology
Mhaboobkhan F1, Aishwarya K2
1Mhaboobkhan F, Department of Electronics & Communication Engineering, P. A. College of Engineering & Technology Pollachi (Tamil Nadu), India.
2Aishwarya K, Department of Electronics & Communication Engineering, Malla Reddy Engineering College for Women, Hyderabad (Telangana), India.
Manuscript received on 15 December 2019 | Revised Manuscript received on 22 December 2019 | Manuscript Published on 31 December 2019 | PP: 132-135 | Volume-9 Issue-1S6 December 2019 | Retrieval Number: A10241291S619/19©BEIESP | DOI: 10.35940/ijeat.A1024.1291S619
Open Access | Editorial and Publishing Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Reduction of power consumption is the major goal in modern circuit design. Reversible logic gate do not lose any information & thus have zero power dissipation. In all signal processing applications, the most important computation involved is Fast Fourier Transform (FFT). For the fault tolerance computation parity preserving logic can be used .The authors present an efficient parity preserving reversible DIF-FFT using 90nm technology. The implementation involves the design of DIF-FFT with reversible P2RG along with Fredkin gate over different combinations of adders (Carry look ahead adder (CLA), Carry save adders (CSA), Carry skip adder (CSK) & Ripple carry adder (RCA)) & multipliers (Array Multiplier (AM), Carry Save Multiplier (CM), Parallel Multiplier (PM), Wallace Tree Multiplier (WM)). DIF-FFT Architectures of different combinations were coded using Verilog & the same was simulated by Modelsim 6.3f. Parameters such as Hardware Device utilization & Power analysis were done using Quartus II 9.0 with respect to Stratix II device which works on 90nm technology. It was found that DIF-FFT Architecture designed using CSA & CM uses lesser resource utilization whereas architecture designed using CSA & AM has lesser Power dissipation by 72% & 81% respectively.
Keywords: DIF-FFT, Parity Preserving Logic, Fredkin Gate, P2RG.
Scope of the Article: Microstrip Antenna Design and Application