Area and Delay Efficient Compressor Based Montgomery Multiplier
G. Revathi1, K. V. Gowreesrinivas2, P. Samundiswary3
1G.Revathi, Department of Electronics Engineering, Pondicherry University, Puducherry, India.
2K.V.Gowreesrinivas, Department of Electronics Engineering, Pondicherry University, Puducherry, India.
3P.Samundiswary, Department of Electronics Engineering, Pondicherry University, Puducherry, India.
Manuscript received on July 20, 2019. | Revised Manuscript received on August 25, 2019. | Manuscript published on August 30, 2019. | PP: 2720-2727 | Volume-8 Issue-6, August 2019. | Retrieval Number: F8273088619/2019©BEIESP | DOI: 10.35940/ijeat.F8273.088619
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Modular multiplication plays an important role in public-key crypto-systems. It first performs integer multiplication and then the costlier division operation is done. Due to this, the computation time and resource requirements will be high. In order to overcome these limitations, Montgomery Modular Multiplication (MMM) method is widely used. As integer multiplication is the most important operation in the Montgomery Multiplication algorithm, it becomes mandatory to enhance the speed of Integer Multiplier (IM) so that it can increase the overall efficiency of Montgomery Multiplier (MM). This work is mainly focused on compressor based MM to improve the performance in respect to propagation delay and area. In this paper, MM using 3:2, 4:2 and 5:2 compressors based Array Multiplier (AM) are designed for performing Integer Multiplication in MM and their performance are evaluated. The modules are synthesized using Xilinx ISE 14.7 and targeted on FPGA family Artix-7. Finally, comparative analysis is made in terms of delay and area.
Keywords: Compressors, ISE, Modular multiplication, Montgomery