FPGA Implementation of Radix-2 based FFT Architecture for Real-Valued signal processing
D.Dinesh kumar1, R.Varun prakash2, G.Kirubakaran3
1D.Dinesh kumar, Dept. of ECE, Mepco Schlenk Engineering College, Sivakasi, India.
2R.Varun prakash, Dept. of ECE, Mepco Schlenk Engineering College, Sivakasi, India.
3G. Kirubakaran, Dept. of ECE, Mepco Schlenk Engineering College, Sivakasi, India.
Manuscript received on July 20, 2019. | Revised Manuscript received on August 10, 2019. | Manuscript published on August 30, 2019. | PP: 596-601 | Volume-8 Issue-6, August 2019. | Retrieval Number: F8073088619/2019©BEIESP | DOI: 10.35940/ijeat.F8073.088619
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper investigates the various pipelined FFT architectures based on radix-2, radix-22 & radix-23 algorithms. The implemented FFTs are designed by employing techniques such as folded transform and register minimization. It maximizes the utilization of hardware resource and reduces the number of adders. It requires less area and achieves high throughput and low latency. For higher values of N, the FFT (Fast Fourier Transform) architecture has many butterfly structures which has been optimized. The FFT outputs are usually obtained in a bit reversed order and a new approach for reordering the bit-reversed orders has been proposed.
Keywords: Bit-reversed order, FFT, Folding Transformation, Redundancy, RFFT.