A Mesoporous Pipelining Scheme for High Performance Digital Systems using Asynchronous Cache
Sukanya. K1, G. Laxminarayana2

1Sukanya. K, Department of Electronics and Communication Engineering, TKR College of Engineering and Technology, Ranga Reddy (Telangana), India.
2G. Laxminarayana, Department of Electronics and Communication Engineering, TKR College of Engineering and Technology, Ranga Reddy (Telangana), India. 

Manuscript received on 13 June 2017 | Revised Manuscript received on 20 June 2017 | Manuscript Published on 30 June 2017 | PP: 283-286 | Volume-6 Issue-5, June 2017 | Retrieval Number: E5099066517/17©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: To relate the increasing behavior of processor and main memory in economical manner, new cache designs and implementations are essential. Cache is liable for themain part of energy consumption. This paper presents an implementation of mesochronous pipelined scheme for high performance digital circuit using asynchronouscache. As a result of the real fact that design of cache memory is time consuming and error prone manner, configurable and synthesizable model generates a particular variety of caches in reproducible and speedy fashion. The mesochronous pipelined cache, implemented by C-Elements which act as a disseminated message passing system. The RTL cache model is implemented in 8×8 multiplier circuit in this paper contains large amount of data and instruction caches and it has a wide array of configurable parameters. Finally, the proposed model produces low delay, reduced area and low power consumption compared to the existing 8 bit multiplication process.
Keywords: Mesochronous Pipelined, Asynchronous Cache, Delay, Area, Power Consumption, 8 Bit Multiplier, RTL Model

Scope of the Article: Low-power design