FPGA Implementation of Frame Decoding Behaviour of Flex Ray Communication Protocol
Deepa M Raju1, Abraham C G2, V Suresh Babu3
1Ms. Deepa M Raju, Electronics and Communication Engineering, St. Joseph’s College of Engineering and Technology, Palai.
2Mr. Abraham C G, Electronics and Communication Engineering, St. Joseph’s College of Engineering and Technology, Palai.
3Dr. V Suresh Babu, Electronics and Communication Engineering, College of Engineering Trivandrum, Palai.
Manuscript received on July 21, 2014. | Revised Manuscript received on August 06, 2014. | Manuscript published on August 30, 2014. | PP: 109-114 | Volume-3 Issue-6, August 2014. | Retrieval Number: F3335083614/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper has highlighted the concept of Frame decoding behaviour of Flex Ray Communication Protocol. The VHDL model of Flex Ray frame decoder of Flex Ray Communication Controller is designed. The design is simulated using Model Sim Altera Edition 13.0 and synthesized using Quartus II 22.214.171.124. The frame decoding behaviour is implemented using Stratix IV GX FPGA. This project design is made with the intention of development of low power; high performance FPGA for decoding the data transmitted which will be a basic for the development of Flex Ray communication controller.
Keywords: Area Efficient, FPGA, Low power, VHDL Language.