Design and Implementation of Extended Version of AES Algorithm with DSP Units
Sagar Deshpande1, Leelavathi G.2
1Mr. Sagar Deshpande, VLSI Design and Embedded System, VTU Extension Center, UTL Technologies Ltd, Bangalore, India.
2Mrs. Leelavathi G, VLSI Design and Embedded System, VTU Extension Center, UTL Technologies Ltd, Bangalore, India.
Manuscript received on July 21, 2013. | Revised Manuscript received on August 19, 2013. | Manuscript published on August 30, 2013. | PP: 360-364 | Volume-2, Issue-6, August 2013.  | Retrieval Number: F2103082613/2013©BEIESP

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Abstract: Advanced Encryption Standard (AES), also known as Rijndael, is a block cipher algorithm that has been analyzed extensively and is now used widely. The AES algorithm hardware implementation is faster and more secure than software implementation. AES algorithm is used to encrypt and decrypt data as this can make the whole process much faster and secured communication is also established in the system. This is also extended to 176 and 192 bits in this work. Hardware implementation of Advanced Encryption Standard (AES) algorithm has been in intensive discussion since its first publication by National Institute of Standards and Technology (NIST) in 2000, for higher throughput over 1 Giga bits per second (Gbps). However, the studies of low power, low area and low cost implementations, which normally have throughput less than 1Gbps and use the data path less than 32-bit, have recently appeared in ASIC as well as in FPGA for wireless communication and embedded hardware application. In the proposed work the encryption of 128,176 and 192 bits are aimed for accurate AES implementation. This proposed work has been divided into two main phases software development and hardware development. In the development of software, it is involved with writing the code, simulation process with Xilinx 13.2 ISE tool. The hardware development covers the Xilinx Spartan 6 FPGA target board development. An AES cipher implementation that is based on the Block RAM and DSP units embedded within Xilinx’s Spartan-6 FPGAs. An iterative “basic” module outputs a 32 bit column of an AES round in each clock cycle, with the throughput of 1.76 Gbits when processing a 128 bit inputs, one 176 bits data and 192 bits data. Finally, the “round” module is replicated ten times for a fully unrolled design that yields over 55 Gbits of throughput. High throughput implementations are mainly used for high-end devices such as accelerator cards for e-commercial service and security trunk communications. In order to achieve higher performance in today’s utilization of hardware accelerators for cryptography algorithms and heavily loaded communication networks is more efficient.