Design of 128- bit Kogge-Stone Low Power Parallel Prefix VLSI Adder for High Speed Arithmetic Circuits
P. Annapurna Bai1, M. Vijaya Laxmi2
1 P. Annapurna Bai, Master of Technology, M. Tech in DECS at Sree kalahasteeswara Institute of Technology, Srikalahasti, (Andhra Pradesh), India.
2Mrs. M. Vijaya laxmi, M.E, Associate Professor in ECE Department of Sree kalahasteeswara Institute of Technology, Srikalahasti, (Andhra Pradesh), India.
Manuscript received on July 21, 2013. | Revised Manuscript received on August 14, 2013. | Manuscript published on August 30, 2013. | PP: 415-418 | Volume-2, Issue-6, August 2013. | Retrieval Number: F2084082613/2013©BEIESP
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Abstract: Parallel Prefix adders have been one of the most notable among several designs proposed in the past. The advantage of utilizing the flexibility in implementing the three structures based upon throughput requirements. Due to continuing integrating intensity and the growing needs of portable devices, low-power and high-performance designs are of prime importance. The classical parallel prefix adder structures presented in the literature over the years optimize for logic depth, area, and fan-out and interconnect count of logic circuits. In this paper, a new architecture for performing 128-bit Parallel Prefix addition is proposed. In this proposed system kogge-stone adder which is one of types of parallel prefix adder is used. Kogge-stone is the fastest adder because of its minimum fan-out. The proposed 128-bit prefix adder is compared with classical adders of same bit width in terms of power, delay. The results reveal that the proposed 128-bit Parallel Prefix adder has the least power delay product when compared with its peer existing adder structures (ripple carry adder, carry save adders). Simulation results are verified using Xilinx 14.3 software.
Keywords: Dot operator, Power delay product, Kogge-stone, Carry save adder, fan-out.