An Implementation on 32-Bit High Speed Truncation- Error -Tolerant Adder with Low power Consumption
Tadgiri Aruna1, R.Bhadraiah2
1Tadgiri Aruna, M. Tech, Nimra College Of Engineering & Technology, Jupudi, Ibrahimpatnam (Mandal), Vijayawada, Krishna, India.
2R.Bhadraiah, M. Tech, Assistant Professor, Nimra College Of Engineering & Technology Jupudi, Ibrahimpatnam (Mandal), Vijayawada, Krishna, India.
Manuscript received on July 23, 2013. | Revised Manuscript received on August 05, 2013. | Manuscript published on August 30, 2013. | PP: 305-309 | Volume-2, Issue-6, August 2013. | Retrieval Number: F2070082613/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this study, we had proposed architecture for high speed Truncation Adder Algorithm. In modern VLSI technology, the occurrence of all kinds of errors has become inevitable. By adopting an emerging concept in VLSI design and test, error tolerance (ET), a novel error-tolerant adder (ETA) is proposed. The ETA is able to ease the strict restriction on accuracy, and at the same time achieve tremendous improvements in both the power consumption and speed performance. When compared to its conventional counterparts, the proposed ETA is able to attain more than 74% improvement. One important potential application of the proposed ETA is in digital signal processing systems that can tolerate certain amount of errors. The modifications to the conventional shift and add multiplier includes introduction of modified error tolerant technique for addition and enabling of adder cell by current multiplication bit of the multiplier constant.
Keywords: High speed arithmetic, error tolerant technique, image processing, power dissipation, Digital Signal Processing (DSP), Least Significant Bit (LSB), adder cells, high-speed integrated circuits, low-power design, VLSI.