Implementation of Canny Edge Detection Algorithm on FPGA and displaying Image through VGA Interface
Chaithra.N.M.1, K.V. Ramana Reddy2
1Chaithra.N.M, VLSI Design and Embedded Systems, Visveswaraiah Technological University, VTU Extension Centre, UTL Technologies Ltd. Bangalore, India.
2Asst. Prof K.V. Ramana Reddy, VLSI Design and Embedded Systems, Visveswaraiah Technological University VTU Extension Centre, UTL Technologies Ltd. Bangalore, India.
Manuscript received on July 22, 2013. | Revised Manuscript received on August 06, 2013. | Manuscript published on August 30, 2013. | PP: 243-247 | Volume-2, Issue-6, August 2013. | Retrieval Number: F2053082613/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Edge detection is one of the most important stages in image processing. The Canny edge detection algorithm is most widely used edge detection algorithm because of it advantages. In this paper we present canny edge detection algorithm implemented on Spartan 3E FPGA and developed VGA interfacing for displaying images on the screen. In this paper we have taken 128×128 Image and displayed same on the monitor through FPGA.
Keywords: Block Memory, Canny, FPGA, VGA Interface.