Design and Implementation of Kogge Stone adder using CMOS and GDI Design: VLSI Based
S. Vasantha Swaminathan1, J. Surendiran2, B. P. Pradeep Kumar3
1Dr. S. Vasantha Swaminathan, Professor, Department of ECE, Malla Reddy Engineering College for Women Autonomous, Secunderabad (Telangana), India.
2J. Surendiran, Professor, Department of ECE, HKBHCE, Bangaluru (Karnataka), India.
3B. P. Pradeep Kumar, Associate Professor, Department of ECE, HKBHCE, Bangaluru (Karnataka), India.
Manuscript received on 01 November 2019 | Revised Manuscript received on 13 November 2019 | Manuscript Published on 22 November 2019 | PP: 2181-2182 | Volume-8 Issue-6S3 September 2019 | Retrieval Number: F14220986S319/19©BEIESP | DOI: 10.35940/ijeat.F1422.0986S319
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Abstract: Adders is a significant part in different math legitimate activity. Parallel Prefix Adder was developed as the most basic and effective circuit for double expansion. The Particular structure and execution are alluring for VLSI usage. In these papers, I can depict the structure and execution of the Kogge Stone Parallel Prefix Adders and actualized utilizing diverse plan procedure. CMOS (Complementary Metal Oxide Semiconductor) and GDI (Gate Diffusion Input) are the distinctive structure system utilized. . The plan and reenactment of rationale entryways is performed on CADENCE Design Suit 6.1.6 utilizing virtuoso and ADE Environment at GPDK 180nm innovation. The execution estimation considered for the presentation of the KSA is delay, number of door check/Transistor Count (territory) and power. Recreation reads are accomplished for 4-piece, 8-piece and 16-piece input information.
Keywords: Parallel Prefix Adder, Kogge Stone Adder, CMOS plan, GDI structure, Cadence Design Suite, 180nm innovation, Area, Power, Delay and Power Delay Product.
Scope of the Article: Computer Architecture and VLSI