Design of Area Efficent 32 Bit Arithmetic and Logic Unit (ALU) for DSP Processors
K. V. Ganesh1, V. Malleswara Rao2, Sreenivasa Rao Ijjada3
1K. V. Ganesh, Senior Member, IEEE, Assistant Professor, Department of ECE, VITAM College of Engineering, (Andhra Pradesh), India.
2Dr. V. Malleswara Rao, Senior Member, IEEE, Professor, Department of ECE, GITAM University, Visakhapatnam (Andhra Pradesh), India.
3Sreenivasa Rao Ijjada, Senior Member, IEEE, Assistant Professor, Department of ECE, GIT, GITAM University, Visakhapatnam (Andhra Pradesh), India.
Manuscript received on 28 September 2019 | Revised Manuscript received on 10 November 2019 | Manuscript Published on 22 November 2019 | PP: 1270-1278 | Volume-8 Issue-6S3 September 2019 | Retrieval Number: F12190986S319/19©BEIESP | DOI: 10.35940/ijeat.F1219.0986S319
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Abstract: Almost every electronic gadget contains the Digital signal processor (DSP) unit for the purpose of computations, whose role couldn’t be specified with smaller words. Gadget’s performance, efficiency and the importance could be measured with how best the specifications of the processors are. Arithmetic and Logical Unit (ALU) is the key circuit for any DSP processors, where large data computations can be performed. Hence, the ALUs design should be include high performance and large data handling capacity. An ALU is a digital electronic circuit that performs arithmetic and bitwise operations on integer binary numbers. The conventional ALU designs, design complexity rate proportionally increases with the performance demand. In this paper, an attempt has been given to design a low complex ALU with improved performance. Sub circuits designs comprise with new approaches to make the simple designs for higher performance of ALU. A 32 bit ALU design procedure has been demonstrated in this paper. For design, 90 nm CMOS technology and CADENCE virtuoso tools used.
Keywords: Arithmetic And Logical Unit, Adders, Multipliers, Digital Signal Processing, Multiplexers, Comparators.
Scope of the Article: Digital System and Logic Design