A New ALU Design using PNS-FCR: Static CMOS Logic for Microprocessors
T. Subhashini1, M. Kamaraju2, K. Babulu3
1T.Subhashini, Scholor, Department of ECE, JNTUK, Kakinada (Andhra Pradesh), India.
2M.Kamaraju, Department of ECE, GEC, Gudlavalleru (Andhra Pradesh), India.
3K.Babulu, Department of ECE, Kakinada (Andhra Pradesh), India.
Manuscript received on 15 September 2019 | Revised Manuscript received on 24 September 2019 | Manuscript Published on 10 October 2019 | PP: 876-882 | Volume-8 Issue-6S2, August 2019 | Retrieval Number: F12150886S219/19©BEIESP | DOI: 10.35940/ijeat.F1215.0886S219
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Arithmetic Logic Unit (ALU) is the main component in the processors. Most important design consideration in integrated circuit is power. In all the components of ALU data path is the active one and it consumes more percent of power in the total power. In the modern microprocessors it is important to have power efficient data paths. To reduce the power consumption in microprocessors the ALU is designed using PNS-FCR static CMOS logic. In this paper static CMOS logic is used to reduce power consumption. Static technique does not need any clock. So it leads to less power consumption. For the implementation of the ALU with the PNS-FCR static logic mentor graphics tool is used. The power consumption of ALU is compared with and without using FCR. An 8-bit ALU is designed in mentor graphics with 130nm technology. The proposed design methodology gives less power consumption.
Keywords: PNS-FCR, Static CMOS Logic, ALU.
Scope of the Article: Digital System and Logic Design