Implementation of Logic Fault Detection Techniques using FPGA
N. Mohana Sundaram1, S. Arun Kumar2, A. Mahalingam3
1N. Mohana Sundaram, Assistant Professor, Kumaraguru College of Technology, Coimbatore (Tamil Nadu), India.
2S. Arun Kumar, Assistant Professor, Kumaraguru College of Technology, Coimbatore (Tamil Nadu), India.
3A. Mahalingam, Assistant Professor, Sri Shakthi Institute of Engineering and Technology, Coimbatore (Tamil Nadu), India.
Manuscript received on 28 September 2019 | Revised Manuscript received on 10 November 2019 | Manuscript Published on 22 November 2019 | PP: 1231-1237 | Volume-8 Issue-6S3 September 2019 | Retrieval Number: F12110986S319/19©BEIESP | DOI: 10.35940/ijeat.F1211.0986S319
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Abstract: The evolution of automation concept in industries and rising significance for digital mode of communication have in turn stresses the need for reliable, efficient and high performance digital system. One of the major problems faced in the digital transmission is the loss of data and hence an effective technique to detect and correct these faults is necessary. Conventionally, various techniques are used for this purpose. Among them, three of the techniques like Plain Majority Logic (ML) Decoder, Syndrome Fault Detector and Plain ML Detector Decoder (MLDD) are analyzed and compared in this paper. The purpose of this comparison is to identify the most suitable methodology based on its capability to track maximum number of faults in minimum number of cycles, with reduced memory read access time. All these logics are simulated using HDL code and analysis is done to implement it in FPGA. The results reveal that Plain MLDD is found to provide better solution for various digital circuits than other techniques.
Keywords: Majority Logic Decoder (MLD), Syndrome Fault Detector (SFD), Majority Logic Detector Decoder (MLDD).
Scope of the Article: FPGAs