Design and FPGA Implementation of Systolic Array Architecture for Matrix Multiplication
Rakesh Birle1, Lalit Bandil2
1Rakesh Birle, [Mtech IVth Sem] Specialization in embedded system & vlsi, AITS Academy, Indore (M.P.) India.
2Lalit Bandil, Associate Professor Dept. of Electronics and Communication Engg, AITS Academy, Indore (M.P.) India.
Manuscript received on July 17, 2012. | Revised Manuscript received on August 25, 2012. | Manuscript published on August 30, 2012. | PP: 252-254 | Volume-1 Issue-6, August 2012.  | Retrieval Number: F0682081612/2012©BEIESP

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Abstract: Matrix multiplication is the kernel operation used in many image and signal processing applications. This paper demonstrates an effective design for the Matrix Multiplication using Systolic Architecture. This architecture increases the computing speed by using the concept of parallel processing and pipelining into a single concept. The selected platform is a FPGA (Field Programmable Gate Array) device since, in systolic computing, FPGAs can be used as dedicated computers in order to perform certain computations at very high frequencies. The description language used as an entry tool to model the hardware architecture is VERILOG HDL. 
Keywords: FPGA implementation, Matrix multiplication, Systolic Arrays, VERILOG HDL