Implementation of Carry-Save Adders in FPGA
S. Ravi Chandra Kishore1, K.V. Ramana Rao2
1S. Ravi Chandra Kishore, M.Tech ECE Department, JNTU Kakinada University/ Pydah College of Engineering and Tehnology/Visakhapatnam, India.
2K.V. Ramana Rao, Assoc.Professor & Head, Dept. of ECE, Pydah College of Engineering & Technology, India.
Manuscript received on July 17, 2012. | Revised Manuscript received on August 25, 2012. | Manuscript published on August 30, 2012. | PP: 27-29 | Volume-1 Issue-6, August 2012.  | Retrieval Number: F0594071612/2012©BEIESP

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Abstract: The addition operations can be optimized through a special purpose carry propagation logic in most of the FPGAs. The delay is same for small size operands and this redundant adders require more hardware resources than carry propagate adders. Therefore, carry-save adders are not usually implemented on FPGA devices, although they are very useful in ASIC implementations. In this paper we have showed that it is possible to implement redundant adders with a hardware cost close to that of a carry propagate adder. Redundant adders are clearly faster for 16 bits and bigger word lengths and have an area requirement similar to carry propagate adders. Among all the redundant adders studied, the 4:2 compressor is the fastest one, presents the best exploitation of the logic resources within FPGA slices and the easiest way to adapt classical algorithms to efficiently fit FPGA resources. This design aimed to be implemented in Spartan-3E FPGA. The CSA architecture uses 1215 LUT’s out of available 3840 and 96 IO blocks and the average fan-out of non clock nets is 4.73 and the peak memory usage is 148 MB. 
Keywords: ASIC, redundant adders, FPGA.