A Mixed Logic Decoder based on FinFET in 32nm Technology
Mohit Sharma1, Rajesh Kumar2

1Mohit Sharma, M. Tech, Scholar, Department of ECE, Sachdeva Institute of Technology, Mathura (affiliated to AKTU Lucknow) (U.P), India.
2Rajesh Kumar, Department of ECE, Sachdeva Institute of Technology, Mathura (affiliated to AKTU Lucknow) (U.P), India.

Manuscript received on 18 June 2019 | Revised Manuscript received on 25 June 2019 | Manuscript published on 30 June 2019 | PP: 2790-2794 | Volume-8 Issue-5, June 2019 | Retrieval Number: E7728068519/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: In this paper, we present a mixed-logic structure technique with the utilization of FinFET technology for line decoders 2 to 4 and 4 to 16 mode, joining the fundamental transmission gate logic, the pass transistor dual-esteem logic and base CMOS logic. To setups are considered and investigated which are 14T and 15T, 14T is for low power and low transistor check advantage and 15T is for superior as far as power and delay. FinFET turns out to be magnificent substitute of mass MOSFET. Likewise, as per analysts the short channel impacts are essentially decreased in FinFET, the consequences of the decoders are contrasted and the MOSFET partner. The technology hubs taken is 32nm as short channel impacts increment the power utilization and superfluous exchanging in the circuit. It is seen that the power, PDP and Voltage Source Power Dissipation are improved in the circuit by about 97%, 98% and 99% individually with same however lower delays.
Keywords: Decoder, FinFET, Short Gate, Power

Scope of the Article: Fuzzy Logics