An Adiabatic Logic and Transmission Gate Logic Based Topology for Low Power SRAM
Atul Kumar1, Rajesh Kumar2

1Atul Kumar, (M.Tech Scholar) ECE Departmet, Sachdeva Institute of Technology, Mathura (U.P), India.
2Rajesh Kumar, ECE Departmet, Sachdeva Institute of Technology, Mathura (U.P), India.

Manuscript received on 18 June 2019 | Revised Manuscript received on 25 June 2019 | Manuscript published on 30 June 2019 | PP: 2022-2025 | Volume-8 Issue-5, June 2019 | Retrieval Number: E7723068519/19©BEIESP
Open Access | Ethics and Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (

Abstract: In this paper, we propose a rapid, low power scattering, low average power consumption and low PDP (Power Delay Product) based SRAM cell. SRAM cell assume a significant job away gadgets and henceforth it is important to deliver a superior structure for the ideal use in the compact gadgets. The MOSFET based customary 6 T SRAM has high power and postpone item with high short direct impacts in 32nm innovation. Henceforth, an answer is given by the utilization of adiabatic logic and transmission gate logic. In this system, we utilize a transistor among Vdd and Virtual Vdd to improve the qualities, it demonstrates that Average power is diminished by 94.75%, delay is improved by 87.15%, power dispersal is improved by 88.78% and vitality is diminished by 99.19% in adiabatic proposed circuit when contrasted with adiabatic FinFET based circuit and likewise the upgrades in transmission gate based proposed circuit from basic transmission gate FinFET SRAM is improved by 55.24%, 50.28%, 68.63% and 75% on premise of Average Power, Delay, Power Dissipation and Energy. The proposed circuits are of 8 Transistors.
Keywords: Adiabatic, Fin FET, SRAM, Transmission Gate

Scope of the Article: Logic Design