Hardware Efficient LDPC Coding Using Linear Feedback Shift Registers For Secured Transmission
1M.Valarmathi, Department of ECE, SRM, Chennai (Tamil Nadu), India.
2B.Modhini, Department of ECE, SRM, Chennai (Tamil Nadu), India.
Manuscript received on 18 June 2019 | Revised Manuscript received on 25 June 2019 | Manuscript published on 30 June 2019 | PP: 308-311 | Volume-8 Issue-5, June 2019 | Retrieval Number: E6915068519/19©BEIESP
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Abstract: Low Density parity correcting codes are linear error correcting codes, a method of transmitting a message over a noisy channel. The main advantages at LDPC codes are these are reliable and high efficient. In this work LDPC encoder and decoder part of LDPC functioning for compiling a 8-bit message vector and it can be done using verilog code. For secure transmission, LFSR is proposed which provides bit scrambling which is used to encode the information signal at transmission side to make it unintelligible at the receiver side. The output of the LDPC encoder is given to the input of LFSR encoding block which gives the longer information bits called code word. This increases the security, reliability and hardware complexity of the information bits. Decoding is done by Berlekanp-massey algorithm. The proposed LDPC using LFSR encoding design has good performance in which 45 LUT’s are being used instead of 72 LUT’s used in normal LDPC encodes architecture which is optimized with high speed and area.
Keywords: LDPC Using LFSR, Code Word, Berlekanp Massey Algorithm
Scope of the Article: Network Coding