A Novel High Computing Power Efficient VLSI Architectures of Three Operand Binary Adders
Shravan Chintam1, Sai Krishna Marri2, Saidulu Rapolu3, Tejasvey Panchareddy4, Sai Radha Krishan G5
1Chintam Shravan, Department of ECE, RGUKT-Basar, Nirmal Telangana, India.
2Sai Krishna Marri, Department of ECE, RGUKT-Basar, Nirmal, Telangana, India.
3Rapolu Saidulu, Department of ECE, RGUKT-Basar, Nirmal, Telangana, India.
4Panchareddy Tejasvey, Department of ECE, RGUKT-Basar, Nirmal Telangana, India.
5Sai Radha Krishan G, Department of ECE, RGUKT-Basar, Nirmal Telangana, India.
Manuscript received on 20 May 2023 | Revised Manuscript received on 31 May 2023 | Manuscript Accepted on 15 June 2023 | Manuscript published on 30 June 2023 | PP: 61-71 | Volume-12 Issue-5, June 2023 | Retrieval Number: 100.1/ijeat.E41880612523 | DOI: 10.35940/ijeat.E4188.0612523
Open Access | Editorial and Publishing Policies | Cite | Zenodo | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Directly or indirectly adders are the basic elements in almost all digital circuits, three operand adders are the basic building blocks in LCG (Linear congruential generator) based pseudo-random bit generators. Elementary adders are fast, area and power efficient for small bit sizes. Carry save adder computes the addition in O(n) time complexity, due to its ripple carry stage. Parallel prefix adders such as Han-Carlson compute the addition in O(log(n)) time complexity but at the cost of additional circuitry. Hence new high-speed power-efficient adder architecture is proposed which uses four stages to compute the addition, which consumes less power, and the adder delay decreases to O(n/2). Even though it is not much faster than the High-speed Area efficient VLSI architecture of three operand adders (HSAT3), it computes the addition by utilizing less power. The proposed architecture is implemented using Verilog HDL in Xilinx 14.7 design environment and it is evident that this adder architecture is 2 times faster than the carry save adder and 1, 1.5, 1.75 times faster than the hybrid adder structure for 32, 64, 128 bits respectively. Also, power utilization is 1.95 times lesser than HSAT3, 1.94 times lesser than the Han-Carlson adder, and achieves the lowest PDP than the existing three operand techniques.
Keywords: Parallel Prefix Adders, Three Operand Binary Adders.
Scope of the Article: Artificial Intelligence