Design and Implementation of Advanced Encryption Standard Algorithm-128 using Verilog
Vedkiran Saini1, Parvinder Bangar2
1Ms. Vedkiran Saini, Department of ECE, CBS Group of Institution, Jhajjar, India.
2Mr. Parvinder Bangar, CBS Group of Institution, Jhajjar, India.
Manuscript received on May 20, 2014. | Revised Manuscript received on June 16, 2014. | Manuscript published on June 30, 2014. | PP: 265-268  | Volume-3, Issue-5, June 2014.  | Retrieval Number:  E3228063514/2013©BEIESP

Open Access | Ethics and Policies | Cite
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (

Abstract: Security has become an increasingly important feature with the growth of electronic communication. The Symmetric in which the same key value is used in both the encryption and decryption calculations are becoming more popular. AES is a symmetric encryption algorithm processing data in block of 128 bits. Under the influence of a key, a 128-bit block is encrypted by transforming it in a unique way into a new block of the same size. In this paper our main concerns is study AES algorithm and implement all modules of AES algorithm on FPGA. This methodology uses verilog HDL implementation of all the modules of AES algorithm Substitution Bytes Transformation, Shift Rows, Transformation, Mix Columns Transformation, Add Round Key Transformation and present power two different frequency 25 MHz. and 50 Mhz. frequency. The codes have been synthesized using Xilinx ISE 9.1i software for a Virtex 5 FPGA device.
Keywords: Advanced Encryption Standard (AES), Rinjdael, Cryptography.