Design and Verification of UART using System Verilog
Yamini R1, Ramya M V2

1Yamini R*, MTech student, Electronics and communication department, JSSSTU, Mysuru, Karnataka, India.
2Ramya M V, Assistant professor, Electronics and communication department, JSSSTU, Mysuru, Karnataka, India. 

Manuscript received on June 08, 2020. | Revised Manuscript received on June 25, 2020. | Manuscript published on June 30, 2020. | PP: 1208-1211 | Volume-9 Issue-5, June 2020. | Retrieval Number: E1135069520/2020©BEIESP | DOI: 10.35940/ijeat.E1135.069520
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Abstract: The main objective of this paper is to design and verify a full duplex UART module using System Verilog (SV). It is a serial communication protocol which provides communication between the systems without using clock signal. It converts parallel data into serial format and transmits the same. Once the data in serial format is received it is converted into parallel format. Designing of UART includes designing of baud rate generator, receiver, transmitter, interrupt and FIFO modules. Verification involves verifying the design by creating verification environment which allows to reuse the testbench and reduces the code complexity. Randomization is used to check the corner conditions which are hard to reach. 100% assertion and 100% functional coverage is achieved. UART operation is simulated using Questasim software. 
Keywords: UART, SV, BRG, DUT, ASV