Low Power VLSI Architecture for Image Compression System using Discrete Wavelet Transform
Jamuna.M1, A.M.Vijaya Prakash2, J.Pushpanjali3
1Jamuna.M, M.Tech, VLSI DESIGN, Dept of E & C, BIT, Bangalore, India.
2A.M.Vijaya Prakash, Associate. Prof, Dept of E & C, BIT, Bangalore, India.
3J.Pushpanjali, Associate. Prof, Dept of E & C, BIT, Bangalore, India.
Manuscript received on May 17, 2012. | Revised Manuscript received on June 22, 2012. | Manuscript published on June 30, 2012. | PP: 490-495 | Volume-1 Issue-5, June 2012. | Retrieval Number: E0545061512/2012©BEIESP

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Abstract: Image compression has got applications in many fields like digital video, video conferencing and video over wireless networks and internet etc. This paper deals with the implementation of VLSI Architecture of image compression system using low power DWT (Discrete Wavelet Transform). DWT is the most widely used image compression technique and it is the most efficient algorithm used in JPEG image compression. This paper presents implementation of 2 methods of DWT, one is conventional method and the other one is lifting scheme. Since conventional method requires more memory, area and power, lifting scheme is used as an enhanced method. Architecture of the DWT which is a powerful image compression algorithm is implemented using lifting based approach. This architecture enjoys reduced memory referencing¸ related low power consumption¸ low latency and high throughput. The Inverse Discrete Wavelet Transform (IDWT) is also obtained in a similar way to get back the image matrix. The design is implemented in verilog HDL. ISIM is used for the simulation of the design. MATLAB is used as a support for the design for obtaining the input pixels and comparison of the results. CADENCE RTL compiler is used to synthesize and obtain the detailed power and area of the design. 
Keywords: Discrete Wavelet Transform (DWT), Inverse Discrete Wavelet Transform (IDWT), Digital filters.