A Low Power VLSI Architecture for Image Compression System using DCT and IDCT
D.Preethi1, A.M Vijaya Prakash2
1D.Preethi, M.Tech in VLSI Design and Embedded systems, Bangalore Institute of Technology, Bangalore, Karnataka, India.
2A.M.Vijaya Prakash, Associatet. Professor, department of Electronics and communication, Bangalore Institute of Technology, Bangalore.
Manuscript received on May 17, 2012. | Revised Manuscript received on June 22, 2012. | Manuscript published on June 30, 2012. | PP: 363-367 | Volume-1 Issue-5, June 2012. | Retrieval Number: E0544061512/2012©BEIESP

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Abstract: Image compression is an important topic in digital world. It is the art of representing the information in a compact form. This paper deals with the implementation of low power VLSI architecture for image compression system using DCT. Discrete Cosine Transform (DCT) is the most widely used technique for image compression of JPEG images[5] and is a lossy compression method.. The architecture of DCT is based on Lo-effler method[1] which is a fast and low complexity algorithm. In the proposed architecture of DCT multipliers are replaced with adders and shifters. Low power approaches like Canonic signed digit representation for constant coefficients and sub-expression elimination methods has been used. The 2D DCT is performed on 8×8 image matrix using two 1D DCT blocks and a transposition block. Similar to DCT, the IDCT is also implemented using the Lo. effler algorithm for IDCT. Verilog HDL is used to implement the design. ISIM of XILINX is used for the simulation of the design. CADENCE RTL compiler is used to synthesize and obtain the detailed power and area reports of the design. MATLAB is used as the support tool to obtain the input pixel values of the image and the results from both ISIM and MATLAB are compared. 
Keywords: Discrete Cosine Transform (DCT), Low Power, Canonic Signed Digit (CSD), Common Sub expression Elimination (CSE), JPEG, VLSI.