High Speed Codec Design for Crosstalk Avoidance
Sowjanya Sunkara1, T.Ravi Sekhar2
1Sowjanya Sunkara, pursuing MTECH,VLSI, ECE Department, Sree vidyanikethan Engineering college, Tirupathi, India.
2T.RaviSekhar, Assistant professor, ECE Department, Sree vidyanikethan Engineering college, Tirupathi, India.
Manuscript received on may 08, 2012. | Revised Manuscript received on June 10, 2012. | Manuscript published on June 30, 2012. | PP: 161-165 | Volume-1 Issue-5, June 2012 | Retrieval Number: E0457061512/2012©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: The cross talk is dependent on the data transition patterns on the bus, patterns can be classified based on the severity of the crosstalk they impose on the bus. The general idea behind techniques that improve on-chip bus speed is to remove undesirable patterns that are associated with certain classes of crosstalk. Different schemes incur different area overheads since they requires additional wires, spacing between wires or both. We analyze the properties of the FPF-CAC and show that mathematically, a mapping scheme exists between the data words and code words. Our proposed CODEC design offers a near-optimal area overhead performance. An improved version of the CODEC is then presented, which achieves theoretical optimal performance. We also investigate the implementation details of the CODECs, including design complexity and the speed. Optimization schemes are provided to reduce the size of the CODEC and improve its speed.
Keywords: CODEC, FPF-CAC, pruning, shielding.