Design and Implementation of a Memory for Joint Improvement of Error Tolerance and Access Efficiency
Kavya Cheraukula1, Chowdam Venkata Sudhakar2
1CH.kavya, pursuing MTECH,VLSI, ECE Department, Sree vidyanikethan Engineering college, Tirupathi, India.
2C.Venkata sudhakar, Assistant professor, ECE Department, Sree vidyanikethan Engineering college, Tirupathi, India.
Manuscript received on may 13, 2012. | Revised Manuscript received on June 10, 2012. | Manuscript published on June 30, 2012. | PP: 128-131 | Volume-1 Issue-5, June 2012 | Retrieval Number: E0449061512/2012©BEIESP

Open Access | Ethics and  Policies | Cite
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (

Abstract: The on-chip memory becomes increasingly exposed to the dual challenges of device-level reliability degradation and architecture-level performance gap. We propose to exploit the inherent memory soft redundancy for on-chip memory design. Due to the mismatch between fixed cache line size and runtime variations in memory spatial locality, many irrelevant data are fetched into the memory thereby wasting memory spaces. The proposed soft-redundancy allocated memory detects and utilizes these memory spaces for jointly achieving efficient memory access and effective error control. We design an CRC & ECC with error correction techniques by making use of standard Ethernet (004C11DB7H) polynomial and compare with each other, which will be implemented in FPGA proposed system design which take care of the Cache and memory by re-checking the cache when a miss is identified and help in effective functionality of the system and finally we compare which method will give good results in terms of cost and reliability.
Keywords: cache memory, ECC, soft error, URL.