Algorithm for Computation of DCT and its Implementation using a Systolic Architecture
Anamika Jain1, Neeta Pandey2

1Anamika Jain*, ECE department, Maharaja Agrasen Institute of Technology(MAIT) affiliated to GGSIP University,Delhi, India.
2Prof. Neeta Pandey, ECE department, Delhi Technological University(DTU) Delhi University, Delhi, India. 

Manuscript received on March 28, 2020. | Revised Manuscript received on April 25, 2020. | Manuscript published on April 30, 2020. | PP: 2162-2167 | Volume-9 Issue-4, April 2020. | Retrieval Number: D9047049420/2020©BEIESP | DOI: 10.35940/ijeat.D9047.049420
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Abstract: In this paper a new algorithm for computing N-point DCT, where N=4r, r>1 is presented. A new algorithm has been derived that can compute the 1D DCT and it is realized in systolic array that utilizes identical processing elements (PE’s). The proposed approach can be used to obtain other transform like Discrete Sine Transform (DST), Discrete Hartley Transform (DHT). The suggested algorithm requires reduced number of multiplications as compared to the other methods of computing DCT. This suggests structure meets the architectural challenge and it is simple, regular design and cost-effective for special-purpose system.
Keywords: Processing Element, Systolic architecture, DST, DCT, and DHT.