Link State Machine of PCI Express
Rachana S1, Sujatha Hiremath2
1Rachana S*, UG student, ECE Dept, RVCE. Bengaluru, India.
2Sujatha Hiremath, Assistant Professor, ECE Dept, RVCE., Bengaluru, India
Manuscript received on March 30, 2020. | Revised Manuscript received on April 05, 2020. | Manuscript published on April 30, 2020. | PP: 1371-1372 | Volume-9 Issue-4, April 2020. | Retrieval Number: D8478049420/2020©BEIESP | DOI: 10.35940/ijeat.D8478.049420
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: PCI Express is a high-speed serial computer expansion bus standard with advance error reporting technology. It is the common motherboard interface for personal computers’ graphics cards, hard drives, SSDs, Wi-Fi and Ethernet hardware connections. A link in PCIe is the communication path between transmitter and receiver. PCIe operates in all transaction, data link and physical layer. The link bring up in physical layer is essential for the link state machine to proceed further into data transfer state. This paper analyses the Link training and status state machine for the Detect, Polling, Configuration and Recovery states. The state analysis is simulated using the TS1 and TS2 packets transfer between Root Complex and End Point.
Keywords: Root Complex, End Point, State Machine, TS1 & TS2 packets.