Design and Implementation of Braun Multiplier using Parallel Prefix Adders
Siva Chakra Avinash. Bikkina1, Nekkanti.Mouni2

1Siva chakra avinash .b*, ECE ,GITAM deemed to be university ,visakhapatanam,INDIA.
2Nekkanti.mouni, ECE ,GITAM deemed to be university ,visakhapatanam,INDIA.

Manuscript received on March 30, 2020. | Revised Manuscript received on April 05, 2020. | Manuscript published on April 30, 2020. | PP: 1251-1254 | Volume-9 Issue-4, April 2020. | Retrieval Number: D8075049420/2020©BEIESP | DOI: 10.35940/ijeat.D8075.049420
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Abstract: In the recent trends of any application depends on delay and area consumption. The delay and area of consumption are the two important considerations of the industrial. These two parameters are considered for any industry application. This type of application can be developed by the different methods that are used in VLSI technology. The Braun multiplier was developed by two different methods. The CMOS and GDI methods are used to implement this multiplier. The parallel prefix adders are used in the multiplier. Braun multiplier is helpful for increasing the speed of the system. The Braun multiplier is designed in the Tanner V-13 EDA tool. The results of this type of multiplier were considered in both CMOS and GDI.
Keywords: VLSI technology, GDI, CMOS, TANNER EDA