Design and Interfacing of I2C Master with Register and LCD Slaves
A.Sainath Chaithanya1, D.Sindhuja2, D.Bhavana3, P.Vennela4
1A Sainath Chaithanya*, Asst Prof, Department of ECE, RGUKT-Basar, Telangana. India.
2D.Sindhuja, B.Tech, Department of ECE, RGUKT-Basar, Telangana. India.
3D.Bhavana, B.Tech, Department of ECE, RGUKT-Basar, Telangana. India..
4P.Vennela, B.Tech, Department of ECE, RGUKT-Basar, Telangana. India.
Manuscript received on April 11, 2020. | Revised Manuscript received on April 21, 2020. | Manuscript published on April 30, 2020. | PP: 2355-2360 | Volume-9 Issue-4, April 2020. | Retrieval Number: D7901049420/2020©BEIESP | DOI: 10.35940/ijeat.D7901.049420
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: : One of the foremost, well-liked, less sophisticated Serial communication standards, I2C; a bus protocol familiarly meant for the exchange of information among the peripherals residing on the constant circuit card, houses two-wires i.e., data and clock for supporting duplex communication between multiple masters and slaves do considered as prominent and efficient in Data transmission. The present work emphasizes on the I2C controller designed for interfacing with slaves, a simple control register of I2C switches/card where the data is written or scan from, subsequently, I2C core implementation on Spartan 3E FPGA, where one of its on-chip peripheral, in this case LCD treated as a slave for performing data transactions. The entire module is designed in Verilog HDL, functional checking is accomplished with the ISIM 10.0b simulator, followed by the design synthesis using Xilinx ISE14.4 tool.
Keywords: Communication protocols, I2C Bus, I2C Switch, Peripheral interface, SoC, and FPGA.