An FPGA Based Implementation of SIFT Algorithm
T.Kavya1, R .Menaka2
1T. Kavya, Department of Electronics Engineering, VIT Chennai (Tamil Nadu), India.
2R. Menaka, Associate Professor, Department of Electronics Engineering, VIT Chennai (Tamil Nadu), India.
Manuscript received on 18 April 2019 | Revised Manuscript received on 25 April 2019 | Manuscript published on 30 April 2019 | PP: 1193-1198 | Volume-8 Issue-4, April 2019 | Retrieval Number: D6726048419/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Feature extraction is a significant processing step in any machine learning application. The significant features of the image will be extracted to represent different groups for processing. Hence it must be accurately extracted and it should act as a representative for the complete dataset. Feature extraction plays a major role in facilitating the subsequent learning and generalization steps. Scale Invariant Feature Transform (SIFT) is widely used in a variety of applications like surveillance, object recognition, panoramic view generation etc. The SIFT algorithm has a main advantage of its scale and orientation invariance. The steps in SIFT algorithm incurs complex calculations and hence high power for processing. These steps can be parallelized which permits better performance in algorithm execution. This research presents an attempt for parallel implementation of SIFT algorithm in FPGA.
Keywords: FPGA, SIFT, Xilinx, Feature Extraction
Scope of the Article: VLSI Algorithms