FPGA Hardware Co-Simulation of Image Encryption using Hybrid Chaotic Maps Based Stream Cipher
Fadhil Sahib Hasan1, Maryam Amer Saffo2
1Fadhil Sahib Hasan*, Electrical Engineering Department, Mustansiriyah University, Baghdad, Iraq.
2Maryam Amer Saffo, Computer Engineering Department, Al-Farabi University College, Baghdad, Iraq.
Manuscript received on April 05, 2020. | Revised Manuscript received on April 25, 2020. | Manuscript published on April 30, 2020. | PP: 215-225 | Volume-9 Issue-4, April 2020. | Retrieval Number: D6713049420/2020©BEIESP | DOI: 10.35940/ijeat.D6713.049420
Open Access | Ethics and Policies | Cite | Mendeley
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In This paper, new model of image encryption is designed. This model using stream cipher based on finite precision chaotic maps. The model designed in efficient way by using Xilinx System Generator (XSG). Pseudo Random Bit Generator (PRBG) depends on chaotic maps is proposed to design Fixed Point Hybrid Chaotic Map-PRBG (FPHYBCM-PRBG). National Institute of Standards and Technology (NIST) randomness measures tested the randomness of the proposed FPHYBCM-PRBG system. The security analysis, such as histogram, correlation coefficient, information entropy, differential attack (NPCR and UACI) are used to analyze the proposed system. Also, FPGA Hardware Co-Simulation over Xilinx SP605 XC6SLX45T provided to test the reality of image encryption system. The results show that FPHYBCM-PRBG is suitable for image encryption based on stream cipher and outperform some encryption algorithms in sufficient way to enhance the security and robust against brute force attack with low maximum frequency and throughput.
Keywords: Image encryption. Chaotic Maps. Fixed point representation. Stream cipher. Xilinx system generator. FPGA hardware co-simulation.