A Novel Low Power 8-Bit Binary Weighted Charge Steering DAC with Integrated Power Supply using CMOS
Bharathesh Patel N1, Manju Devi2
1Bharathesh patel N*, Assistant Professor, GSSSIETW, Mysore, Department Electrical & Electronics.
2Dr.Manju Devi, Professor, TOCE, Bangalore.
Manuscript received on April 05, 2020. | Revised Manuscript received on April 25, 2020. | Manuscript published on April 30, 2020. | PP: 197-48 | Volume-9 Issue-4, April 2020. | Retrieval Number: D6666049420/2020©BEIESP | DOI: 10.35940/ijeat.D6666.049420
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: : the design and implementation of binary weighted charge steering DAC architectures is discussed in this paper. Charge steering DAC were designed and successfully implemented in CMOS 90nm and 180nm technology. For bigger planning contrasts there is an exchange off between powerful number of bits, and equipment cost and basic way. Taking everything into account, an 8 piece two fold weighted accuse directing DAC of coordinated force supply was effectively planned in 90 and 180nm CMOS innovation utilizing Cadence apparatuses. As indicated by the reproduction results, the proposed DAC is exceptionally straight with the most pessimistic scenario DNL of 0.99LSB and INL of 0.008LSB, and furthermore has low force utilization esteem 96.36mW.
Keywords: DAC, CMOS, DNL, INL.