Analysis of FPGA Based Recursive Filter Using Optimization Techniques for High Throughput
Sunil Kumar Yadav1, Rajesh Mehra2
1Sunil Kumar Yadav, ME Student (ECE), National Institute of Technical Teachers Training and Research, Chandigarh, India.
2Rajesh Mehra, Associate Professor (ECE) National Institute of Technical Teachers Training and Research, Chandigarh, India.
Manuscript received on March 30, 2014. | Revised Manuscript received on April 14, 2014. | Manuscript published on April 30, 2014. | PP: 341-343 | Volume-3, Issue-4, April 2014. | Retrieval Number: D3004043414/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this paper we examine the optimal throughput of recursive filter using varies optimization techniques, which are relevant for real time application. By formulating filter design as a multi-objective optimization problem and approaching. Different approaches use for implementing of these methods on hardware. In this work FPGA implementation of recursive filters are examined and the comparison of these methods is done by analyzing the hardware cost and performance.
Keywords: IIR filter, VHDL, FPGA.