FPGA Based Hardware Implementation of Encryption Algorithm
M. Natheera Banu
M. Natheera Banu, Department of Electronics and Communication, Coimbatore Institute of Engineering And Technology, Coimbatore, Anna University, India.
Manuscript received on November 21, 2011. | Revised Manuscript received on October 01, 2011. | Manuscript published on April 30, 2014. | PP: 271-277  | Volume-3, Issue-4, April 2014. | Retrieval Number:  D2904043414/2013©BEIESP

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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)

Abstract: Reprogrammable devices such as Field Programmable Gate Arrays (FPGA) are used for hardware implementations of cryptographic algorithm. This paper presents an FPGA based Hardware implementation of advanced encryption standard (AES) with 128-bit key as a constant which is used for encrypting the text file and image for secure transmission. Timing report for the files are taken and conclude that text file of 128 bit size is taking less time to encrypt and decrypt compare to the image file. Synthesizing and implementation (Translate, Map and Place and Route) of the VERILOG code is carried out on Xilinx – Project Navigator ISE 12.3 software.
Keywords:  AES, Decryption, Encryption, Image and text.