Evolution & Performance Study of 2D NoC Topologies
Sapna Tyagi1, Amit Agarwal2, Vinay Avasthi3, Piyush Maheshwari4
1Sapna Tyagi, Department of IT, IMT, Ghaziabad (U.P), India.
2Amit Agarwal, Department of Computer Science, University of Petroleum & Energy Studies, Dehradun (Uttarakhand), India.
3Vinay Avasthi, Department of Computer Science, University of Petroleum & Energy Studies, Dehradun (Uttarakhand), India.
4Piyush Maheshwari, Department of Engineering, Amity University, (Dubai) United Arab Emirates.
Manuscript received on 28 March 2019 | Revised Manuscript received on 07 April 2019 | Manuscript Published on 11 April 2019 | PP: 124-129 | Volume-8 Issue-4C, April 2019 | Retrieval Number: D24320484C19/19©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: On chip architectures are adopted as communication infrastructure for System on chip. Various IP cores are integrated on planar chip because of that optimal utilization of resources and reusability can be achieved. The direct link interconnections and shared bus interconnections of SoCs are unable to meet the desired scalability, reliability, and high throughput requirements. The key design considerations and efficiency of NoC as communication infrastructure are dependent on topologies, routing algorithms , low power consumptions and optimum buffer utilization .In our work , the NoC topologies like Torus , Mesh, C-Mesh and Fattree are analyzed . The Parameters used are latency, throughput and hop-count. The comparison presented will help in understanding the topologies empirically. Results presented in the work proved that the torus topology is optimized design and exhibits good trade-off between performances and scalability among the four basic NoC architectures.
Keywords: Booksim 2.0, NoC, System on Chip, Topologies.
Scope of the Article: High Performance Computing