An FSM Based VGA Controller with 640×480 Resolution
Ila.Nagarjuna1, Pillem. Ramesh2
1Nagarjuna. ILA, Pursuing M. Tech in VLSI at K L University, Vijayawada, (A.P), India.
2Pillem. Ramesh, Asst. Professor in K. L. University, Vijayawada, (A.P), India.
Manuscript received on March 12, 2013. | Revised Manuscript received on April 13, 2013. | Manuscript published on April 30, 2013. | PP: 881-885 | Volume-2, Issue-4, April 2013. | Retrieval Number: D1584042413/2013©BEIESP
Open Access | Ethics and Policies | Cite
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Picture caught more attention than verbal voice. A video graphic adapter provides interface between the computer and monitor. The main purpose of this project is to design and implement VGA controller on FPGA. The proposed VGA controller is written based on the block diagram using verilog HDL. Also functions required for the VGA controller are included in the verilog code and test bench is created to test the functions written to ensure the FPGA VGA works correctly and accurately without an errors. This design has display capability supported by a virtually every video adapter on the market, and can be extendable up to 1368×768.we have generated the shapes of coordinate geometry to get in motion, any moving geometric objects can be implemented. The motion can be generated using finite state machines (FSM), with raster pattern from left to right and top to bottom, many shapes can be generated and motion can be in zigzag. We used FILE OUT operations, so that the generated object can be verified before it gets implemented, no need of storage devices like FIFO(leads to complexity with FIFO depth calculations), More economic, we can even check the implementation results without FPGA in static image format. Cadence tool is used for observation and verification in terms of performance. And the code coverage of the design is achieved.
Keywords: Xilinx 12.3, Modelsim SE 6.3f, Spartan3E.