Migration of On-Chip Networks from 2 Dimensional Plane to 3 Dimensional Plane
Naveen Choudhary, Department of Computer Science and Engineering, College of Technology and Engineering, Maharana Pratap University of Agriculture and Technology, Udaipur, Rajasthan, India.
Manuscript received on March 24, 2013. | Revised Manuscript received on April 10, 2013. | Manuscript published on April 30, 2013. | PP: 516-519| Volume-2, Issue-4, April 2013. | Retrieval Number: D1508042413/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In spite of the higher scalability and parallelism presented by 2D-Network-on-Chip (No C) over the conventional shared-bus based systems, it is still not an ultimate solution for future large scale Systems-on-Chip (SoCs). Recently, No C integration in three dimensions is (3D-Network-on-Chip) proposed as a potential solution offering higher speed, low latency, lower dynamic power consumption and high parallelism Advanced integration technologies are making feasible the extension of topology synthesis of on-chip networks from 2 dimension to 3 dimension. Studies have highlighted that 3D No Cs can significantly improve communication efficiency due to reduced communication distances in 3D space. This paper presents a brief journey of research in the domain of Network on Chip topology synthesis from 2D dimensional plane to 3 dimensional plane and highlights the major challenges and issues faced and addressed by the No C research community in the design of 2D standard No Cs, irregular & application specific 2D No Cs and 3D No Cs.
Keywords: Application-Specific-No C, 3D-NoC, 2D-NoC, On-Chip networks, System-on-Chip.