Algorithm for Testing NAND Flash Random Access Memory
G. Lokheshwara Guptha1, M. Anil Kumar2
1G. Lokheshwara Guptha, Department of Electronics and Communication Engineering, K L University, India.
2M. Anil Kumar, Asst Professor, Department of Electronics and Communication Engineering, K L University, India.
Manuscript received on March 02, 2013. | Revised Manuscript received on April 13, 2013. | Manuscript published on April 30, 2013. | PP: 866-869 | Volume-2, Issue-4, April 2013. | Retrieval Number: D1396042413/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper presents an overview of the problem of testing semiconductor random access memories (RAM’s). An important aspect of this test procedure is the detection of permanent faults that cause the memory to function incorrectly. Functional-level fault models are very useful for describing a wide variety of RAM faults. Several Fault models are discussed throughout the paper, including the stuck-at-0/1 faults, coupled-cell faults presented and their fault coverage and execution times are discussed.
Keywords: Algorithms, Reliability, Checking experiments, Fault detection.