Energy Efficient Partitioning Of Last Level Cache Memory with Cooling Management for Memory and CPU Subsystems
Vikash Sharma1, Jayant Kumar2
1Vikash Sharma, M. Tech VLSI, ABV- IITM, Gwalior, India.
2Jayant Kumar, M. Tech VLSI, ABV- IITM, Gwalior, India.
Manuscript received on March 17, 2013. | Revised Manuscript received on April 09, 2013. | Manuscript published on April 30, 2013. | PP: 209-211 | Volume-2, Issue-4, April 2013. | Retrieval Number: D1371042413/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This paper presents a technique to improve the over- all performance of the multiprocessor chip. Efficient partitioning of last- level cache memory in a multi-processor chip can increase the performance significantly. The concept is to first allocate the fixed number of ways for a core and then forced the cache data to be way aligned so that a particular way is owned by a core at a particular time. At the time of access, cores cooperate with each other to migrate the ways between them so that a core has to consult only those ways which it has ownsto find its data from which dynamic energy can be saved and unused ways can be power-gated for saving the static energy. This paper also presents a cooling management strategy for memory and CPU subsystems. It manages the temperature of memory and CPU subsystems by activating the memory and CPU actuators which does the required action in the subsystems of memory and CPU. It considers the thermal and power states of CPU and memory, thermal coupling between them and fan speed to arrive at energy efficient decisions.
Keywords: Last level cache memory (LLC), CPU actuator, Memory actuator, RAP, WAP.