Design and Implementation of FPU for Optimised Speed
R. Bhuvanapriya1, Menakadevi T2

1R. Bhuvanapriya*, P.G. Student, Department of ECE, Adhiyamaan College of Engineering, Hosur, (Tamil Nadu), India.
2Dr. Menakadevi T., Associate Professor, Department of ECE, Adhiyamaan College of Engineering, Hosur, (Tamil Nadu), India.
Manuscript received on January 20, 2020. | Revised Manuscript received on February 05, 2020. | Manuscript published on February 29, 2020. | PP: 3922-3933 | Volume-9 Issue-3, February 2020. | Retrieval Number:  C6444029320/2020©BEIESP | DOI: 10.35940/ijeat.C6444.029320
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Abstract: Currently, each CPU has one or additional Floating Point Units (FPUs) integrated inside it. It is usually utilized in math wide-ranging applications, such as digital signal processing. It is found in places be established in engineering, medical and military fields in adding along to in different fields requiring audio, image or video handling. A high-speed and energy-efficient floating point unit is naturally needed in the electronics diligence as an arithmetic unit in microprocessors. The most operations accounting 95% of conformist FPU are multiplication and addition. Many applications need the speedy execution of arithmetic operations. In the existing system, the FPM(Floating Point Multiplication) and FPA(Floating Point Addition) have more delay and fewer speed and fewer throughput. The demand for high speed and throughput intended to design the multiplier and adder blocks within the FPM (Floating point multiplication)and FPA(Floating Point Addition) in a format of single precision floating point and double-precision floating point operation is internally pipelined to achieve high throughput and these are supported by the IEEE 754 standard floating point representations. This is designed with the Verilog code using Xilinx ISE 14.5 software tool is employed to code and verify the ensuing waveforms of the designed code.
Keywords: FPU, FPM, FPA, IEEE 754, Xilinx ISE.