FPGA Implementation of Efficient FIR Filter
Ranjeeta Yadav1, Rohit Tripathi2, Sachin Yadav3
1Ranjeeta Yadav*, ABES Engineering College,Ghaziabad, INDIA.
2Dr. Rohit Tripathi, Galgotias University, Greater Noida, INDIA.
3Dr. Sachin Yadav, GL Bajaj Institute of Technology & Managment, Greater Noida, INDIA.
Manuscript received on January 26, 2020. | Revised Manuscript received on February 05, 2020. | Manuscript published on February 30, 2020. | PP: 3410-3412 | Volume-9 Issue-3, February 2020. | Retrieval Number: C6349029320 /2020©BEIESP | DOI: 10.35940/ijeat.C6349.029320
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: Improve the functionality of an FIR Filter by modifying the internal components used to design a filter. These past years have seen some great improvements in the speed, power, and area of the filter. Here, we will, therefore, use an ALU-based algorithm to design our FIR filter. The internal components of the ALU block will be an Adder and a Multiplier. A Floating point Adder and a Floating Point Multiplier will be the basic backbone of the ALU block, which finally will be used to design and implement our FIR filter design. Therefore, the parameters of the area are our main target but we will also see the power consumed by the Filter operation, both static and dynamic power consumed will be seen. The programming language will be written in VERILOG and the simulation and implementation of the design will be done by the help of Xilinx ISE suite version. One important aspect is that there will be 16 input samples and 16 coefficients which will be directly from a 16 tap filter. These coefficients and input values will be generated through MATLAB software.
Keywords: IEEE, FIR, Multiplier, ALU, Xilinx