Consideration of Net Weights for Performance Driven Routing
Geetanjali Udgirkar1, G. Indumathi2

1Geetanjali Udgirkar, CMR Institute of Technology, Bangalore (Karnataka), India.
2Dr. G. Indumathi, Cambridge Institute of Technology, Bangalore (Karnataka), India.

Manuscript received on 18 February 2019 | Revised Manuscript received on 27 February 2019 | Manuscript published on 28 February 2019 | PP: 463-467 | Volume-8 Issue-3, February 2019 | Retrieval Number: C5974028319/19©BEIESP
Open Access | Ethics and Policies | Cite | Mendeley | Indexing and Abstracting
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC-BY-NC-ND license (

Abstract: Objectives: In todays’ VLSI technology, interconnect delay is the predominant factor in determining the speed of the final chip. Considering the complexity and size of today’s VLSI designs, timing driven VLSI routing is very challenging problem. Methods/Statistical analysis: The obvious method is to assign weights to the nets of a given route and perform timing driven routing. There are few works in the literature on net-weighting-based timing driven routing. Findings: Based on the criticality of the nets, by assigning weights to the nets in two methods discussed in the paper, we present two novel timing driven routing algorithms. In the first method, a constant is raised to the power of a variable exponent for weight assignment, whereas, in the second method, a variable exponent is raised to the power of a constant. These weights are considered during timing driven VLSI routing for an FPGA using VPR routing tool. Improvements: The proposed methods show significant improvement in timing over VPR routing tool. We obtain improvement of 14.65% and 26.85% using the methods MethodA and MethodB respectively, over VPR.
Keywords: VLSI Routing, Global Routing, Net Weighting Method.

Scope of the Article: VLSI Algorithms