Impact of Threshold Voltage roll off in Ultra Thin Fully Depleted Silicon on Insulator MOSFET
Chandra Shakher Tyagi1, R.L. Sharma2, Prashant Mani3
1Chandra Shakher Tyagi1*, Department of Electronics and Communication Engineering, Noida International University, Noida, U.P. INDIA .
2R.L. Sharma , Department of Electronics and Communication Engineering, Noida International University, Noida, U.P. INDIA.
3Prashant Mani, SRM Institute of Science and Technology, U.P. INDIA.
Manuscript received on May 06, 2020. | Revised Manuscript received on May 15, 2020. | Manuscript published on June 30, 2020. | PP: 1673-1676 | Volume-9 Issue-5, June 2020. | Retrieval Number: C5475029320/2020©BEIESP | DOI: 10.35940/ijeat.C5475.029320
Open Access | Ethics and Policies | Cite | Mendeley
© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: This article is discussing about threshold voltage roll off effect in Ultra Thin Fully Depleted Silicon on Insulator MOSFET. The device performance is improved due to the reduction in threshold voltage roll off. The thickness of oxide layer is optimized to 2nm which also have a vital role in improvement of device’s throughput. The effect of oxide thickness on parasitic parameter also discussed. Device conductance and transconductance also take in account on simulating the ultra thin fully depleted SOIMOSFET.
Keywords: Threshold voltage, SOI, MOSFET, Transconductance .