New Delay and Power Analysis for a CMOS Inverter Driving RLC Interconnect
Sohini Mondal1, Bishnu Prasad De2
1Sohini Mondal, Electronics & Comm. Engg., Haldia Institute Of Technology, Haldia, East Midnapore, India.
2Bishnu Prasad De, Electronics & Comm. Engg., Haldia Institute Of Technology, Haldia, East Midnapore, India.
Manuscript received on January 10, 2013. | Revised Manuscript received on February 01, 2013. | Manuscript published on February 28, 2013. | PP: 430-434| Volume-2 Issue-3, February 2013. | Retrieval Number: C1172022313/2013©BEIESP
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© The Authors. Blue Eyes Intelligence Engineering and Sciences Publication (BEIESP). This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-nc-nd/4.0/)
Abstract: In this era, the on-chip interconnect delay is significantly more dominating than the gate delay. Several approaches have been proposed to capture the interconnect delay accurately and efficiently. Here delay and power analysis for a CMOS inverter driving a resistive-inductive-capacitive load is presented. A closed form delay and power model of a CMOS inverter driving a resistive-inductive-capacitive load is discussed. The model is derived from Sakurai’s alpha-power law and exhibits good accuracy. The model can be used for the design and analysis of the CMOS inverters that drive a large interconnect RLC load when considering both speed and power. Closed form expressions are also presented for the propagation delay and transition time which exhibit less than 15% error compared to the SPICE for a wide range of RLC loads. Explicit methods are also provided for modeling the short-circuit power dissipation of a CMOS inverter driving a RLC line. The average error is within 22% compared to SPICE for most practical loads.
Keywords: Electronics, CMOS, Delay , Power, RLC Interconnect, SPICE,VLSI.